Industry Type : Education / E-Learning / Semiconductor
Functional Area : Training
category: Technical
Filter: Full- time
Job Description
📌 Design Verification Trainer (SV, UVM, VHDL, Verilog)
📌 Physical Design Trainer(PNR, Floor Plan ,CMOS)
📌 Design Trainer (Verilog, VHDL, RTL Coding )
📍 Locations: Bengaluru / Chennai / Hyderabad
⏳ Notice Period: Immediate to 30 Days
Skills Required:
#Design Verification Trainer
RTL Design & Functional Verification
System Verilog & UVM
Assertions, Coverage, and Verification Methodologies
Strong mentoring and communication skills
#Physical Design Trainer
Floor planning, Power Planning
Place & Route (PnR)
CTS, Routing, STA
ICC2/ Innovus and Prime Time
Excellent training and presentation skills
Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools
Extensive experience in Back-end design
Experience on Mentor Graphics EDA flow is an added advantage
Responsible for development and support of Projects.
Responsible for Debugging the source codes in Verilog, SV, and UVM.
Responsible for Training Delivery and Support
Desired Candidate Profile
Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design
3 to 15 + years industry/teaching experience
Good communication & presentation skill